24位定时器, T2/T3/T4增加了8位预分频

ainiw***

另一部分，百度文库里面的无法下载，截屏一部分

32G12***

有最新的数据手册，您可以直接用STC的手册查看

http://www.stcmcudata.com/STC8F-datasheet/STC8H.pdfhttp://www.stcmcudata.com/STC8F-datasheet/STC32G.pdf

jm***

ainiw*** Published on 2023-5-16 17:36
I know this can be automatically generated, I want to refer to the practice in this article,
but according to the above program and circuit block diagram, the cascaded counter and timing...

Where does the circuit design pin connection come from ?
I think that cannot work as connected, because only T0,T1 have INT0,INT1 gating, T3 & T4 timers cannot gate from a INTn pin.
You should instead use T0.T1 as the fastest timers, and cascade out to T3,T4.
ie T0CLKO -> T3, and T1CLKO -> T4 as this connection allows INT0,INT1 to gate the 32bit timer.

Edit: I see the formula assumed this fixed connection, (T0 -> T3, T1 -> T4) but the pin connection drawing is wrong.

There is another problem in the STC timer Pin T1CLKO -> T3 pin chain, which is that T0,T1 overflows toggle the pin, that means two overflows would need to occur to advance T3 or T4.

I think this needs a software fix-up patch: Whenever T0CLKO occurs, use TF0 interrupt to Toggle T0CLKO pin again. (or set it) (likewise for TF1 interrupt to toggle T1CLKO)
eg  T0 = 0xFFFF
T0 pin =\_ causes T0F -> INT, and T0CLK0 toggles =\_, clocking T3.
In order to clock T3 again on the next 0xFFFF, T0CLK0 needs to be returned hi in SW.

ainiw***

jm*** 发表于 2023-6-29 13:55
Where does the circuit design pin connection come from ?
I think that cannot work as connected, be ...

我现在做实验就是遇到这个问题。我查了一下，级联好像是需要同步计数才可以做到。暂时只能用中断的方式进行溢出后累加计数。还没想到其他办法

jm***

ainiw*** Published on 2023-6-29 17:19
This is the problem I am doing experiments now. I checked, and it seems that cascading needs to be counted synchronously. For the time being, it can only be entered in an interrupted way...

I think the overflow problem can be patched with a SW fixup, but since the timer chains are read when disabled, why bother ?

Using two interrupts to increment the high 16 bits of each counter is fine, provided the read is when counter is stopped. The 16b timer overflows are rare, and the int++ is simple.

This also saves two timers, and avoids two external pin bridges for cascade.

It would be nice to also eliminate that external Flip Flop.   
I think that is possible, with a little care, like this  ? :

Using the now-spare timer3 or timer4, you can connect T3CLK0 to INTn_GATE of T0,T1 (replaces FF Q )
To Start Counter GATE you preload T3 to 0xFFFF, and enable T3 to Frequency in, with T3CLKO = LOW.
Then T3R=1 will toggle T3CLKO high on the next Fi =\_, enabling the counters.

T3INT:   // Interrupt toggles T3CLKO on next Fin edge, after T3R is set elsewhere
T3R = 0
T3 = 0xFFFF

After the ~ 1 second window, you enable T3R again, and this time the next Fi =\_, disables the counters, and you can read the values. - Whole cycles in, and time for those whole cycles

Summary: Every T3R enable, enables a delayed output change on T3CLKO, which is triggered by Fi =\_, so this emulates the external D Flip Flop.

The spare Timer4  + prescaler, could be used for self-test option, by frequency generate on T4CLKO, jumper to Fin for testing.


The highest Fin when using T0,T3 pins will be limited to maybe ~ < sysclk/2, so an external small MCU (SO16 or TSSOP20) could be used as a prescaler.
eg the STC8H1K08 has XTALI pin which can be AC coupled, and it can /N to MCLKO pin.
A single pin and a few lines of code would select between CLKDIV = /1 and /50 on that external prescaler.
Based on tests with other vendor's 8051s that's probbly good to ~ 200MHz Fin ? (needs CLKDIV > 5 for MCU to run code )

I'm not sure how to handle out of range Fin, or how XITYPE affects upper Pin bandwidth ?

ainiw***

jm*** 发表于 2023-6-30 04:35
I think the overflow problem can be patched with a SW fixup, but since the timer chains are read wh ...

按您所说的理解，这样操作也要用到中断吧，定时器溢出时产生中断，再改变一次T0CLKO的电平状态以满足产生一次使T3计数+1？不知道我理解的对不对。
我是想将
频率信号1->[T0和INT0]->T0CLKO->T3级联直接计数,  而不用再在中断中操作改变一下T0CLKO状态.
频率信号2->[T1和INT1]->T1CLKO->T4级联直接计数，而不用再在中断中操作改变一下T0CLK1状态.

jm***

ainiw*** 发表于 2023-6-30 23:14
按您所说的理解，这样操作也要用到中断吧，定时器溢出时产生中断，再改变一次T0CLKO的电平状态以满足产生 ...

Yes, because T0CLKO toggles on every 0xFFFF -> 0x0000 the first overflow does =\_ and then the next one does _/= but only one of those edges advances T3, so the counter is not a correct 32 bits.

You can patch this  problem by change of the not-counting edge : If 0xFFFF -> 0x000 gives =\_ that advances T3, so the TF0 interrupt then flips T0CLKO back to HI, (ignored by T3)  and then next 0xFFFF -> 0x0000 now will correctly toggle T3, as needed.

However, if you have already created an interrupt, you idea of software increment of the upper 16 bits is smarter.
It works the same, there is a lot of time allowed for the SW increment, and int16++ is very fast.
That frees up timers for more useful things, like removing the external FlipFlop and creating test frequencies.

32G12***

星***

功能越来越强大了

cdp***

要是能计数值能达到连续24位就更好了. 或用2个16位可以拼成一个32位计数器.