练习下驱动FLASH储存模块/W25Q32

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最近研究lcd


官方历程没字库 需要自己下到flash  买个W25Q32研究下

8毛钱到手

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问客服没有中文文档

英文的

开始吧

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1 /CS  芯片选择
2 DO（IO1）I/O数据输出（数据输入输出1)(1)
3 /WP（IO2）I/O写保护输入（数据输入输出2)*2
4 GND
5 DI（IO0）I/O数据输入
6 CLK I串行时钟输入
7 通信 I/O保持或重置输入
8 VCC

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cs引脚  为高时 芯片没被选择  为低时 被选择 可以进行数据读写   必须开机为高

4.1 Chip Select (/CS)
The SPI Chip Select (/CS) pin enables and disables device operation. When /CS is high the device is
deselected and the Serial Data Output (DO, or IO0, IO1, IO2, IO3) pins are at high impedance. When
deselected, the devices power consumption will be at standby levels unless an internal erase, program or
write status register cycle is in progress. When /CS is brought low the device will be selected, power
consumption will increase to active levels and instructions can be written to and data read from the device.
After power-up, /CS must transition from high to low before a new instruction will be accepted. The /CS
input must track the VCC supply level at power-up and power-down (see “Write Protection” and Figure 58).
If needed a pull-up resister on the /CS pin can be used to accomplish this.

4.1芯片选择（/CS）SPI芯片选择（/CS）引脚可启用和禁用设备操作。当/CS很高时，设备被取消选择，并且串行数据输出（DO，或IO0、IO1、IO2、碘酸盐）引脚处于高阻抗。当取消选择时，设备的功耗将处于待机状态，除非正在进行内部擦除、程序或写状态寄存器周期。当/CS降低时，将选择设备，功耗将增加到活动水平，可以写入指令并从设备读取数据。上电后，/CS必须从高到低，才能接受新的指令。/CS输入必须在通电和断电时跟踪VCC电源水平（请参见“写入保护”和图58)。如果需要，可以使用/CS销上的上拉阻力来完成这一点。

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W25Q32JV支持标准SPI、双SPI和Quad SPI操作。 我们用单片机双相通信spi

4.2 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3)
The W25Q32JV supports standard SPI, Dual SPI and Quad SPI operation. Standard SPI instructions use
the unidirectional DI (input) pin to serially write instructions, addresses or data to the device on the rising
edge of the Serial Clock (CLK) input pin. Standard SPI also uses the unidirectional DO (output) to read data
or status from the device on the falling edge of CLK.
Dual and Quad SPI instructions use the bidirectional IO pins to serially write instructions, addresses or data
to the device on the rising edge of CLK and read data or status from the device on the falling edge of CLK.
Quad SPI instructions require the non-volatile Quad Enable bit (QE) in Status Register-2 to be set. When
QE=1, the /WP pin becomes IO2 and the /HOLD pin becomes IO3.

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其他的也没啥    说明书  需要的可以自己去读下

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我们把 wp和hold全部接到vcc  关闭读写保护和一直保持通信


开时测试去了

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32Mb的就是4M做中文字库完全足够啊

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配置玩 io和spi  下面看下指令集

Write Enable 06h