25.SPI读写W25X40CL - 按k1（20251026已经解决）

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7.15. Quad Page Program (32H)

The Quad Page Program command is forprogramming the memory using four pins: IO0, IO1, IO2, and IO3. To use QuadPage Program the Quad enable in status register Bit9 must be set (QE=1). AWrite Enable (WREN) command must previously have been executed to set the WriteEnable Latch (WEL) bit before sending the Page Program command. The quad PageProgram command is entered by driving CS# Low, followed by the command code(32H), three address bytes and at least one data byte on IO pins.

The command sequence is shown in Figure19.If more than 256 bytes are sent to the device, previously latched data arediscarded and the last 256 data bytes are guaranteed to be programmed correctlywithin the same page. If less than 256 data bytes are sent to device, they arecorrectly programmed at the requested addresses without having any effects onthe other bytes of the same page. CS# must be driven high after the eighth bitof the last data byte has been latched in; otherwise the Quad Page Program (PP)command is not executed.

As soon as CS# is driven high, theself-timed Quad Page Program cycle (whose duration is tPP) is initiated. While the Quad PageProgram cycle is in progress, the Status Register may be read to check thevalue of the Write In Progress (WIP) bit. The Write in Progress (WIP) bit is 1during the self-timed Quad Page Program cycle, and is 0 when it is completed.At some unspecified time before the cycle is completed, the Write Enable Latch(WEL) bit is reset.

A Quad PageProgram command applied to a page which is protected by the Block Protect (BP4,BP3, BP2, BP1, and BP0) is not executed.

7.15.四页编程指令 (32H) 四页编程指令用于通过四根线IO0、IO1、IO2 和 IO3 来编程内存。要使用四页编程，状态寄存器 Bit9 中的四页使能（QE=）必须设置。在发送页面编程指令之前，必须先执行写使能（WREN）命令以设置写使能锁存器（WEL）位。页编程指令通过将 CS# 拉低，然后是命令代码（32H）、三个地址字节和至少一个数据字节进入 IO 引脚。 序列如图19所示。如果向设备发送超过256字节的数据，之前锁存的数据将被丢弃，并且保证最后256个数据字节在同一内正确编程。如果向设备发送的数据字节少于256个，它们将在请求的地址处正确编程，并且不会对同一页面中的其他字节产生任何。在最后数据字节的第八位被锁存后，必须将 CS# 拉高；否则，四页编程（PP）命令将不被执行。 一旦# 被拉高，自定时四页编程周期（其持续时间为 tPP）即启动。当四页编程周期正在进行时，可以读取状态寄存器检查写操作进行中（WIP）位的值。在自定时四页编程周期期间，写操作进行中（WIP）位为1，完成后为0在周期完成之前某个未指定的时间，写使能锁存器（WEL）位被复位。 应用于受块保护（BP4、BP3、2、BP1 和 BP0）保护的页面的四页编程命令将不被执行。

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7.16. Sector Erase (SE) (20H)

The Sector Erase (SE) command is used toerase all the data of the chosen sector. A Write Enable (WREN) command mustpreviously have been executed to set the Write Enable Latch (WEL) bit. TheSector Erase (SE) command is entered by driving CS# low, followed by thecommand code, and 3-address byte on SI. Any address inside the sector is avalid address for the Sector Erase (SE) command. CS# must be driven low for theentire duration of the sequence.

The Sector Erasecommand sequence: CS# goes low à sending Sector Erase command à 3-byte address on SI à CS# goes high. The command sequence is shown in Figure21.CS# must be driven high after the eighth bit of the last address byte has beenlatched in; otherwise the Sector Erase (SE) command is not executed. As soon asCS# is driven high, the self-timed Sector Erase cycle (whose duration is tSE) is initiated. While the Sector Erasecycle is in progress, the Status Register may be read to check the value of theWrite in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during theself-timed Sector Erase cycle, and is 0 when it is completed. At someunspecified time before the cycle is completed, the Write Enable Latch (WEL)bit is reset. A Sector Erase (SE) command applied to a sector which isprotected by the Block Protect (BP4, BP3, BP2, BP1, and BP0) bit (seeTable1&1a) is not executed.

7.16. 扇区擦除（SE）（20H）

扇区擦除（SE）命令用于除所选扇区中的所有数据。在执行该命令之前，必须先执行写使能（WREN）命令以设置写使能寄存器（W）位。扇区擦除（SE）命令通过将CS#拉低，然后发送命令代码和3个地址字节（在SI上）来输入。扇内的任何地址都是扇区擦除（SE）命令的有效地址。在整个序列期间，CS#必须保持低电平。

扇区擦除命令序列：CS拉低  发送扇区擦除命令  SI上的3字节地址  CS#拉高。命令序列如图21所示。在最后一个地址字第八位被锁存后，CS#必须被拉高；否则，扇区擦除（SE）命令将不被执行。一旦CS#被拉高，自扇区擦除周期（其持续时间为tSE）即启动。在扇区擦除周期进行过程中，可以读取状态寄存器以检查写操作进行（IP）位的值。在自定时扇区擦除周期期间，写操作进行（WIP）位为1，完成后为0。在周期完成之前某个未时间，写使能寄存器（WEL）位被复位。当扇区受到块保护（BP4、BP3、BP2、BP1和BP）位保护时（见表1&1a），扇区擦除（SE）命令将不被执行

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7.17. 32KB Block Erase (BE) (52H)

The 32KB Block Erase (BE) command is usedto erase all the data of the chosen block. A Write Enable (WREN) command mustpreviously have been executed to set the Write Enable Latch (WEL) bit. The 32KBBlock Erase (BE) command is entered by driving CS# low, followed by the commandcode, and three address bytes on SI. Any address inside the block is a validaddress for the 32KB Block Erase (BE) command. CS# must be driven low for theentire duration of the sequence.

The 32KB BlockErase command sequence: CS# goes low à sending 32KB Block Erase command à 3-byte address on SI à CS# goes high. The command sequence is shown in Figure22.CS# must be driven high after the eighth bit of the last address byte has beenlatched in; otherwise the 32KB Block Erase (BE) command is not executed. Assoon as CS# is driven high, the self-timed Block Erase cycle (whose duration istBE) is initiated. While the Block Erasecycle is in progress, the Status Register may be read to check the value of theWrite in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during theself-timed Block Erase cycle, and is 0 when it is completed. At someunspecified time before the cycle is completed, the Write Enable Latch (WEL)bit is reset. A 32KB Block Erase (BE) command applied to a block which isprotected by the Block Protect (BP4, BP3, BP2, BP1, and BP0) bits (seeTable1&1a) is not executed.

7.17. 32KB 块擦除（BE）（52H）

32KB 块除（BE）命令用于擦除所选块中的所有数据。在执行该命令之前，必须先执行写使能（WREN）命令以设置写使能存器（WEL）位。通过将 CS# 拉低，然后发送命令代码和三个地址字节，即可输入 32KB 块擦除（）命令。块内的任何地址都是 32KB 块擦除（BE）命令的有效地址。在整个序列期间，CS# 必须保持低电平。32KB 块擦除命令序列：CS# 拉低  发送 32KB 块擦除命令  SI 上的 3 地址  CS# 拉高。命令序列如图22所示。在最后一个地址字节的第八位被锁存后，必须将 CS# 拉高；，32KB 块擦除（BE）命令将不会执行。一旦 CS# 被拉高，自定时 Block Erase 周期（其持续时间为 t）即开始。当 Block Erase 周期正在进行时，可以读取状态寄存器以检查 Write in Progress（WIP）位的值。在自定时 Block Er 周期期间，Write in Progress（WIP）位为 1，完成后为 0。在周期完成之前，某个未指定的时间点，Write Enable Latch（EL）位被复位。当块受到 Block Protect（BP4、BP3、BP2、BP1 和 BP0）位保护时（见表1&;1a），32KB 块擦除（BE）命令将不会执行。

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7.18. 64KB Block Erase (BE) (D8H)

The 64KB Block Erase (BE) command is usedto erase all the data of the chosen block. A Write Enable (WREN) command mustpreviously have been executed to set the Write Enable Latch (WEL) bit. The 64KBBlock Erase (BE) command is entered by driving CS# low, followed by the commandcode, and three address bytes on SI. Any address inside the block is a valid addressfor the 64KB Block Erase (BE) command. CS# must be driven low for the entireduration of the sequence.

The 64KB BlockErase command sequence: CS# goes low à sending 64KB Block Erase command à 3-byte address on SI à CS# goes high. The command sequence isshown in Figure23. CS# must be driven high after the eighth bit of the lastaddress byte has been latched in; otherwise the 64KB Block Erase (BE) commandis not executed. As soon as CS# is driven high, the self-timed Block Erasecycle (whose duration is tBE) is initiated. While the Block Erase cycle is inprogress, the Status Register may be read to check the value of the Write inProgress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timedBlock Erase cycle, and is 0 when it is completed. Atsome unspecified time before the cycle is

completed, the Write Enable Latch (WEL) bit is reset. A 64KB BlockErase (BE) command applied to a block which is protected by the Block Protect(BP4, BP3, BP2, BP1, and BP0) bits (see Table1&1a) is not executed.

7.18. 64KB BlockErase (BE) (D8H) 64KB块擦（BE）命令用于擦除所选块中的所有数据。在执行64KB块擦除（BE）命令之前，必须先执行写使能（WREN命令以设置写使能寄存器（WEL）位。通过将CS#拉低，然后发送命令代码和三个地址字节，通过SI输入64块擦除（BE）命令。块内的任何地址都是64KB块擦除（BE）命令的有效地址。CS#在整个序列期间必须保持低电平 64KB块擦除命令序列：CS#拉低 发送64KB块擦除命令 SI上的3字节地址 #拉高。命令序列如图23所示。CS#必须在最后一个地址字节的第八位被锁存后拉高；否则，64KB块擦除（）命令将不被执行。一旦CS#被拉高，自定时块擦除周期（其持续时间为tBE）即启动。当块擦除周期正在进行时可以读取状态寄存器以检查写操作进行（WIP）位的值。在自定时块擦除周期期间，写操作进行（WIP）位为，完成后为0。在周期完成之前，写使能寄存器（WEL）位被复位。应用于由块保护（BP4、BP3、BP、BP1和BP0）位保护的块（见表1&1a）的64KB块擦除（BE）命令不会被执行

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7.19. Chip Erase (CE) (60/C7H)

The Chip Erase (CE) command is used toerase all the data of the chip. A Write Enable (WREN) command must previouslyhave been executed to set the Write Enable Latch (WEL) bit .The Chip Erase (CE)command is entered by driving CS# Low, followed by the command code on SerialData Input (SI). CS# must be driven Low for the entire duration of thesequence.

The Chip Erasecommand sequence: CS# goes low à sending Chip Erase command à CS# goes high. The command sequence is shown in Figure21.CS# must be driven high after the eighth bit of the command code has beenlatched in; otherwise the Chip Erase command is not executed. As soon as CS# isdriven high, the self-timed Chip Erase cycle (whose duration is tCE) is initiated. While the Chip Erase cycleis in progress, the Status Register may be read to check the value of the Writein Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during theself-timed Chip Erase cycle, and is 0 when it is completed. At some unspecifiedtime before the cycle is completed, the Write Enable Latch (WEL) bit is reset.The Chip Erase (CE) command is executed only if all Block Protect (BP2, BP1,and BP0) bits are 0. The Chip Erase (CE) command is ignored if one or moresectors are protected.

7.19. 芯片擦除 (CE) (60/C7H) 芯片擦除 (CE)命令用于擦除芯片中的所有数据。在执行该命令之前，必须先执行写使能 (WREN) 命令以设置写使能寄存器 (EL) 位。芯片擦除 (CE) 命令通过将 CS# 拉低，然后通过串行数据输入 (SI) 发送命令代码来输入。在整个操作过程中，CS# 必须保持低电平。 芯片擦除命令序列：CS# 拉低  发送芯片擦除命令  CS#拉高。命令序列如图21所示。在命令代码的第八位被锁存后，CS# 必须被拉高；否则，芯片擦除命令将执行。一旦 CS# 被拉高，自定时钟的芯片擦除周期 (其持续时间为 tCE) 将被启动。在芯片擦除周期进行过程中可以读取状态寄存器以检查写操作进行 (WIP) 位的值。在自定时钟的芯片擦除周期内，写操作进行 (WIP 位为1，完成后为0。在周期完成之前的不确定时间点，写使能寄存器 (WEL) 位将被复位。 只有所有块保护 (BP2、BP1 和 BP0) 位都为0时，才会执行芯片擦除 (CE) 命令。如果一个或多个扇受到保护，芯片擦除 (CE) 命令将被忽略。

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7.20. Deep Power-Down (DP) (B9H)

Executing the Deep Power-Down (DP) commandis the only way to put the device in the lowest consumption mode (the DeepPower-Down Mode). It can also be used as an extra software protectionmechanism, while the device is not in active use, since in this mode, thedevice ignores all Write, Program and Erase commands. Driving CS# highdeselects the device, and puts the device in the Standby Mode (if there is nointernal cycle currently in progress). But this mode is not the Deep Power-DownMode. The Deep Power-Down Mode can only be entered by executing the DeepPower-Down (DP) command. Once the device has entered the Deep Power-Down Mode,all commands are ignored except the Release from Deep Power-Down and ReadDevice ID (RDI) command. This releases the device from this mode. The Releasefrom Deep Power-Down and Read Device ID (RDI) command also allows the Device IDof the device to be output on SO.

The DeepPower-Down Mode automatically stops at Power-Down, and the device alwaysPower-Up in the Standby Mode. The Deep Power-Down (DP) command is entered bydriving CS# low, followed by the command code on SI. CS# must be driven low forthe entire duration of the sequence.

TheDeep Power-Down command sequence: CS# goes low à sending Deep Power-Down command à CS# goes high. The command sequence is shown inFigure22. CS# must be driven high after the eighth bit of the command code hasbeen latched in; otherwise the Deep Power-Down (DP) command is not executed. Assoon as CS# is driven high, it requires a delay of tDP before the supply currentis reduced to ICC2andthe Deep Power-Down Mode is entered. Any Deep PowerDown (DP) command, while anErase, Program or Write cycle is in progress, is rejected without having anyeffects on the cycle that is in progress.

7.20. 深度低功耗模式 (DP) (B9H) 执行深度低功耗模式 () 命令是使设备进入最低功耗模式 (深度低功耗模式) 的唯一方法。它也可以用作额外的软件保护机制，当设备不处于活动使用状态时因为在此模式下，设备忽略所有写、编程和擦除命令。将CS# 置高会取消选择设备，并将设备置于待机模式(如果没有当前进行的内部周期)。但此模式不是深度低功耗模式。深度低功耗模式只能通过执行深度低功耗 (DP) 命令进入。一旦设备进入深度低模式，除了释放深度低功耗和读取设备 ID (RDI) 命令外，所有命令都会被忽略。此命令将设备从该模式中释放。释放低功耗和读取设备ID (RDI) 命令还允许设备ID 输出到SO。 深度低功耗模式在关断时自动停止，设备始终在机模式下启动。深度低功耗 (DP) 命令通过将 CS# 置低，然后跟随 SI 上的命令代码来输入。CS# 在整个序列必须保持低电平。 深度低功耗命令序列：CS# 变低 发送深度低功耗命令 CS# 变高。命令如图22所示。在命令代码的第八位被锁存后，CS# 必须被拉高；否则，深度低功耗 (DP) 命令不会执行一旦 CS# 被拉高，它需要在 tDP 后将供应电流减少到 ICC2 并进入深度低功耗模式。任何深度低功耗 (DP)命令，当擦除、编程或写周期正在进行时，都会被拒绝，并且不会对正在进行的周期产生任何影响

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7.21. Release from Deep Power-Down or HighPerformance Mode and Read Device ID (RDI) (ABH)

The Release from Power-Down or HighPerformance Mode / Device ID command is a multi-purpose command. It can be usedto release the device from the Power-Down state or High Performance Mode orobtain the devices electronic identification (ID) number.

To release the device from the Power-Downstate or High Performance Mode, the command is issued by driving the CS# pinlow, shifting the instruction code “ABH” and driving CS# high as shown inFigure26. Release from Power-Down will take the time duration of tRES1 (See AC Characteristics) before the devicewill resume normal operation and other command are accepted. The CS# pin mustremain high during the tRES1 time duration.

When used only to obtain the Device IDwhile not in the Power-Down state, the command is initiated by driving the CS#pin low and shifting the instruction code “ABH” followed by 3-dummy byte. TheDevice ID bits are then shifted out on the falling edge of SCLK with mostsignificant bit (MSB) first as shown in Figure27. The Device ID value is listedin Manufacturer and Device Identification table. The Device ID can be readcontinuously. The command is completed by driving CS# high.

When used torelease the device from the Power-Down state and obtain the Device ID, thecommand is the same as previously described, and shown in Figure27, except thatafter CS# is driven high it must remain high for a time duration of tRES2 (See AC Characteristics). After this timeduration the device will resume normal operation and other command will beaccepted. If the Release from Power-Down / Device ID command is issued while anErase, Program or Write cycle is in process (when WIP equal 1) the command isignored and will not have any effects on the current cycle.

7.21. 从深度低功耗或高性能模式释放并读取设备ID（RDI）（ABH）从低功耗或高性能模式释放/设备ID命令是一个多功能命令。它可以用来使设备从低功耗状态或高性能模式中释放，或者获取设备的电子识别（ID号。 为了使设备从低功耗状态或高性能模式中释放，需要通过将CS#引脚拉低，移位指令代码“ABH”，然后将#引脚拉高来发送命令，如图26所示。从低功耗状态释放需要tRES1的时间（见交流特性），然后设备才会恢复正常操作并其他命令。在tRES1时间段内，CS#引脚必须保持高电平。 当仅用于获取设备ID，且设备不在低功耗状态时，的启动是通过将CS#引脚拉低，移位指令代码“ABH”，然后跟随3个占位字节。然后，设备ID位在SCLK下降沿上移出，最高有效位（MSB）首先移出，如图27所示。设备ID值在制造商和设备识别表中列出。设备ID连续读取。命令通过将CS#引脚拉高而完成。 当用于从低功耗状态释放设备并获取设备ID时，命令与之前描述的一致，27所示，只是当CS#被拉高后，它必须保持高电平一段时间tRES2（见交流特性）。在此时间段之后，设备将恢复正常并接受其他命令。如果在擦除、编程或写周期正在进行时（当WIP等于1时）发出从低功耗状态释放/设备ID命令，命令将被，并且不会对当前周期产生任何影响。

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7.22. Read Manufacture ID/ Device ID(REMS) (90H)

The Read Manufacturer/Device ID command isan alternative to the Release from Power-Down / Device ID command that providesboth the JEDEC assigned Manufacturer ID and the specific Device ID.

The command isinitiated by driving the CS# pin low and shifting the command code “90H”followed by a 24-bit address (A23-A0) of 000000H. After which, the ManufacturerID and the Device ID are shifted out on the falling edge of SCLK with mostsignificant bit (MSB) first as shown in Figure28. If the 24-bit address isinitially set to 000001H, the Device ID will be read first.

7.22. 读取制造商 ID/设备 ID（REMS）(90H) 读取制造商/设备 ID 命令是自掉电/设备 ID 命令的替代命令，它提供了 JEDEC 分配的制造商 ID 和特定的设备 ID。 通过将 CS# 引脚拉并随后移位命令代码“90H”和 24 位地址（A23-A0）000000H 来启动命令之后，制造商 ID 和设备 ID 在 SCLK 的下降沿上按最高有效位（MSB）优先移出，如图28所示。如果 24位地址最初设置为 000001H，则首先读取设备 ID。

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7.23. Read Identification (RDID) (9FH)

The Read Identification (RDID) commandallows the 8-bit manufacturer identification to be read, followed by two bytesof device identification. The device identification indicates the memory typein the first byte, and the memory capacity of the device in the second byte.The Read Identification (RDID) command while an Erase or Program cycle is inprogress is not decoded, and has no effect on the cycle that is in progress.The Read Identification (RDID) command should not be issued while the device isin Deep Power-Down Mode.

The device isfirst selected by driving CS# to low. Then, the 8-bit command code for thecommand is shifted in. This is followed by the 24-bit device identification,stored in the memory, being shifted out on Serial Data Output, each bit beingshifted out during the falling edge of Serial Clock. The command sequence isshown in Figure 31. The Read Identification (RDID) command is terminated bydriving CS# to high at any time during data output. When CS# is driven high,the device is put in the Standby Mode. Once in the Standby Mode, the devicewaits to be selected, so that it can receive, decode and execute commands.

7.23. 读取识别 (RDID) (9FH) 读取识别 (RDID) 命令允许8位制造商识别码，然后是两个字节的设备识别码。设备识别码的第一个字节表示内存类型，第二个字节表示设备的内存容量。当擦除编程周期正在进行时，读取识别 (RDID) 命令不被解码，并且对正在进行的周期没有影响。在设备处于深度低功耗模式时，不应发送读取 (RDID) 命令。 设备首先通过将 CS# 驱动为低电平来选择。然后，将命令的 8 位命令代码移入。之后是存储在内存中的 24 位设备识别码，通过串行数据输出移出，每个位在串行时钟的下降沿期间移出。序列如图31所示。在数据输出期间，读取识别 (RDID) 命令通过在任何时候将 CS# 驱动为高电平来终止。当 CS 被驱动为高电平时，设备进入待机模式。一旦进入待机模式，设备将等待被选择，以便它可以接收、解码和执行命令

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7.24. High Performance Mode (HPM) (A3H)

The HighPerformance Mode (HPM) command must be executed prior to Dual or Quad I/Ocommands when operating at high frequencies (see fC2 and fC3 in AC Electrical Characteristics). Thiscommand allows pre-charging of internal charge pumps so the voltages requiredfor accessing the flash memory array are readily available. The commandsequence: CS# goes lowàSending A3H commandà Sending 3-dummy byteàCS# goes high. See Figure32. After the HPM command is executed, the devicewill maintain a slightly higher standby current (Icc8) than standard SPIoperation. The Release from Power-Down or HPM command (ABH) can be used toreturn to standard SPI standby current (Icc1). In addition, Power-Down command(B9H) will also release the device from HPM mode back to standard SPI standbystate.

7.24. 高性能模式 (HPM) (A3H) 当在较高频率下操作时 (参见 电气特性中的 fC2 和 fC3)，必须在 Dual 或 Quad I/O 命令之前执行高绩效模式 (HPM) 命令。此允许内部充电泵的预充电，以便访问闪存阵列所需的电压随时可用。命令序列：CS# 变低发送 A3H 命令 3 个占位字节CS# 变高。参见图32。 在执行 HPM 命令后，设备将保持比标准 SPI 操作高的待机电流 (Icc8)。可以使用 Release from Power-Down 或 HPM 命令 (ABH) 返回到标准 SPI 待机电流Icc1)。此外，Power-Down 命令 (B9H) 也将使设备从 HPM 模式返回到标准 SPI 待机状态