25.SPI读写W25X40CL - 按k1（20251026已经解决）

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7.5. Write Enable for Volatile StatusRegister (50H)

The non-volatile Status Register bits canalso be written to as volatile bits. This gives more flexibility to change thesystem configuration and memory protection schemes quickly without waiting forthe typical non-volatile bit write cycles or affecting the endurance of theStatus Register non-volatile bits. The Write Enable for Volatile StatusRegister command must be issued prior to a Write Status Register command, andany other commands cannot be inserted between them. Otherwise, Write Enable forVolatile Status Register will be cleared. The Write Enable for Volatile StatusRegister command will not set the Write Enable Latch bit, it is only valid forthe Write Status Register command to change the volatile Status Register bitvalues.

7.5. 易失性状态寄存器写使能（50H） 非易失性状态寄存器也可以作为易失性位写入。这提供了更多的灵活性，可以在不等待典型的非易失性位写周期或影响状态寄存器非易失性位的久性的情况下快速改变系统配置和内存保护方案。在写状态寄存器命令之前必须发出易失性状态寄存器写使能命令，并且它们不能插入任何其他命令。否则，易失性状态寄存器写使能将被清除。易失性状态寄存器写使能命令不会设置写使锁存位，它仅对写状态寄存器命令有效，以改变易失性状态寄存器位值。

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7.6. Read Data Bytes (READ) (03H)

The Read DataBytes (READ) command is followed by a 3-byte address (A23-A0), each bit beinglatched-in during the rising edge of SCLK. Then the memory content, at thataddress, is shifted out on SO, each bit being shifted out, at a Max frequency fR, during the falling edge of SCLK. The first byteaddressed can be at any location. The address is automatically incremented tothe next higher address after each byte of data is shifted out. The wholememory can, therefore, be read with a single Read Data Bytes (READ) command.Any Read Data Bytes (READ) command, while an Erase, Program or Write cycle isin progress, is rejected without having any effects on the cycle that is inprogress.

7.6. 读取数据字节（READ）(03H) 读取数据字节（READ）命令后跟一个3字节地址A23-A0），每个位在SCLK上升沿时被锁存。然后，该地址处的内存内容通过SO移出，每个位在CLK下降沿时以最大频率fR移出。第一个字节地址可以位于任何位置。数据字节移出后，地址自动递增到下一个更高地址。，整个内存可以通过单个读取数据字节（READ）命令进行读取。当擦除、编程或写操作正在进行时，任何读取数据字节（READ）命令将被拒绝并且对正在进行的操作没有影响。

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7.7. Read Data Bytes at Higher Speed (FastRead) (0BH)

The Read DataBytes at Higher Speed (Fast Read) command is for quickly reading data out. Itis followed by a 3-byte address (A23-A0) and a dummy byte, each bit beinglatched-in during the rising edge of SCLK. Then the memory content, at thataddress, is shifted out on SO, each bit being shifted out, at a Max frequency fC, during the falling edge of SCLK. The first byteaddressed can be at any location. The address is automatically incremented tothe next higher address after each byte of data is shifted out.

7.7. 以较高速度读取数据字节（快速读取）(0BH) 以较高速度读取数据字节（快速读取）用于快速读取数据。它后面跟一个3字节地址（A23-A0）和一个虚拟字节，每个位在SCLK上升沿时被锁存然后，在SCLK下降沿时，以最大频率fC将内存内容从该地址移出到SO，每个位在SCLK下降沿时移出。第一个字节地址可以位于任何位置。数据字节移出后，地址自动递增到下一个更高地址。

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7.8. Dual Output Fast Read (3BH)

The Dual Output Fast Read command is followed by 3-byteaddress (A23-A0) and a dummy byte, each bit being latched in during the risingedge of SCLK, then the memory contents are shifted out 2-bit per clock cyclefrom SI and SO. The command sequence is shown in followed Figure 9. The firstbyte addressed can be at any location. The address is automatically incrementedto the next higher address after each byte of data is shifted out

7.8. 双输出快速读取（3BH）

双输出快速读取命令后跟3字节地址（A23-A0和一个空字节，每个位在SCLK上升沿时被锁存，然后内存内容从SI和SO每时钟周期移出2位。

命令序列如图所示。第一个字节地址可以在任何位置。数据字节移出后，地址自动递增到下一个更高地址。

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7.9. Quad Output Fast Read (6BH)

The Quad OutputFast Read command is followed by 3-byte address (A23-A0) and a dummy byte, eachbit being latched in during the rising edge of SCLK, then the memory contentsare shifted out 4-bit per clock cycle from IO3, IO2, IO1 and IO0. The commandsequence is shown in followed Figure10. The first byte addressed can be at anylocation. The address is automatically incremented to the next higher addressafter each byte of data is shifted out.

7.9. 四线输出快速读取（6BH） 四线输出快速读取命令后跟3字节地址（A23-0）和一个空字节，每个位在SCLK上升沿时被锁存，然后内存内容从IO3、IO2、IO1和IO0每时钟移出4位。命令序列如图10所示。第一个字节地址可以在任何位置。数据字节移出后，地址自动递增到下一个更高地址

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7.10. Dual I/O Fast Read (BBH)

The Dual I/O Fast Read command is similarto the Dual Output Fast Read command but with the capability to input the3-byte address (A23-0) and a “Continuous Read Mode” byte 2-bit per clock by SIand SO, each bit being latched in during the rising edge of SCLK, then thememory contents are shifted out 2-bit per clock cycle from SI and SO. Thecommand sequence is shown in followed Figure11. The first byte addressed can beat any location. The address is automatically incremented to the next higheraddress after each byte of data is shifted out.

Dual I/O Fast Read with “Continuous ReadMode”

The Dual I/O FastRead command can further reduce command overhead through setting the“Continuous Read Mode” bits (M7-0) after the input 3-byte address (A23-A0). Ifthe “Continuous Read Mode” bits (M7-0) =AXH, then the next Dual I/O Fast Read command(after CS# is raised and then lowered) does not require the BBH command code.The command sequence is shown in followed Figure11. If the “Continuous ReadMode” bits (M7-0) are any value other than AXH, the next command requires thefirst BBH command code, thus returning to normal operation. A “Continuous ReadMode” Reset command can be used to reset (M7-0) before issuing normal command.

7.10. 双I/O快速读取（BBH） 双I/O快速读取命令与双输出读取命令类似，但具有通过SI和SO输入3字节地址（A23-0）和“连续读取模式”字节的能力，每个时钟由SI和SO2位，每位的时钟上升沿被锁存，然后内存内容从SI和SO每时钟周期移出2位。命令序列如图11所示。第一个字节可以位于任何位置。数据字节移出后，地址自动递增到下一个更高地址。 具有“连续读取模式”的双I/O快速读取 通过在3字节地址（A23-A0）后设置“连续读取模式”位（M7-0），双I/O快速读取命令可以进一步减少开销。如果“连续读取模式”位（M7-0）=AXH，那么下一个双I/O快速读取命令（在CS#上升然后下降）不需要BBH命令代码。命令序列如图11所示。如果“连续读取模式”位（M7-0）的值不是AXH，那么下一个命令需要BBH命令代码，从而返回到正常操作。可以使用“连续读取模式”复位命令在发出正常命令之前重置（M7-0）

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7.11. Quad I/O Fast Read (EBH)

The Quad I/O Fast Read command is similarto the Dual I/O Fast Read command but with the capability to input the 3-byteaddress (A23-0) and a “Continuous Read Mode” byte and 4-dummy clock 4-bit perclock by IO0, IO1, IO2, IO3, each bit being latched in during the rising edgeof SCLK, then the memory contents are shifted out 4-bit per clock cycle fromIO0, IO1, IO2, IO3. The command sequence is shown in followed Figure13. Thefirst byte addressed can be at any location. The address is automaticallyincremented to the next higher address after each byte of data is shifted out.The Quad Enable bit (QE) of Status Register (S9) must be set to enable for theQuad I/O Fast read command.

Quad I/O Fast Read with “Continuous ReadMode”

The Quad I/O FastRead command can further reduce command overhead through setting the“Continuous Read Mode” bits (M7-0) after the input 3-byte address (A23-A0). Ifthe “Continuous Read Mode” bits (M7-0) =AXH, then the next Quad I/O Fast Readcommand (after CS# is raised and then lowered) does not require the EBH commandcode. The command sequence is shown in followed Figure13. If the “ContinuousRead Mode” bits (M7-0) are any value other than AXH, the next command requiresthe first EBH command code, thus returning to normal operation. A “ContinuousRead Mode” Reset command can be used to reset (M7-0) before issuing normalcommand.

7.11. 四线I/O快速读取（EBH） 四线I/O快速读取命令双线I/O快速读取命令类似，但具有输入3字节地址（A23-0）和“连续读取模式”字节以及每个时钟4个虚拟时钟的能力，由IO0、IO1、IO2、IO3每时钟4位，每个位在SCLK上升沿时被锁存，然后内存内容从IO、IO1、IO2、IO3每时钟周期移出4位。命令序列如图13所示。第一个字节地址可以在任何位置。数据字节移出后地址自动递增到下一个更高地址。状态寄存器（S9）的四线使能位（QE）必须设置为使能，以使四线I/快速读取命令生效。 具有“连续读取模式”的四线I/O快速读取 四线I/O快速读取命令可以通过在输入3字节地址（A3-A0）后设置“连续读取模式”位（M7-0）来进一步减少命令开销。如果“连续读取模式”位（M70）=AXH，那么下一个四线I/O快速读取命令（在CS#上升然后下降之后）不需要EBH命令代码。命令序列如图13。如果“连续读取模式”位（M7-0）的值不是AXH，那么下一个命令需要第一个EBH命令代码，从而返回到正常操作。“连续读取模式”复位命令来重置（M7-0），然后再发出正常命令。

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7.12. Quad I/O Word Fast Read (E7H)
The Quad I/O Word Fast Read command is similar to the Quad I/O Fast Read command except that the lowest address bit (A0) must equal 0 and only 2-dummy clock. The command sequence is shown in followed Figure15. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The Quad Enable bit (QE) of Status Register (S9) must be set to enable for the Quad I/O Word Fast read command.
Quad I/O Word Fast Read with “Continuous Read Mode”
The Quad I/O Word Fast Read command can further reduce command overhead through setting the “Continuous Read Mode” bits (M7-0) after the input 3-byte address (A23-A0). If the “Continuous Read Mode” bits (M7-0) =AXH, then the next Quad I/O Word Fast Read command (after CS# is raised and then lowered) does not require the E7H command code. The command sequence is shown in followed Figure15. If the “Continuous Read Mode” bits (M7-0) are any value other than AXH, the next command requires the first E7H command code, thus returning to normal operation. A “Continuous Read Mode” Reset command can be used to reset (M7-0) before issuing normal command.

7.12. 四线I/O字快速读取（E7H） 四线I/O字快速命令与四线I/O快速读取命令类似，只是最低地址位（A0）必须等于0，并且只有2个空闲时钟。命令序列如图1所示。第一个字节地址可以位于任何位置。每个字节的数据移出后，地址会自动递增到下一个更高的地址。状态寄存器（S9）的四使能位（QE）必须设置为使能，以使四线I/O字快速读取命令生效。 具有“连续读取模式”的四线I/O字快速读取 通过在输入3字节地址（A23-A0）后设置“连续读取模式”位（M7-0），四线I/O快速读取命令可以进一步减少命令开销。如果“连续读取模式”位（M7-0）=AXH，那么在CS#上升然后下降之后，四线I/O字快速读取命令就不需要E7H命令代码。命令序列如图15所示。如果“连续读取模式”位（M7-0的值不是AXH，那么下一个命令需要第一个E7H命令代码，从而返回到正常操作。可以使用“连续读取模式”复位命令来重置（7-0），然后再发出正常命令。

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7.13. Set Burst with Wrap (77H)

The Set Burst with Wrap command is used inconjunction with “Quad I/O Fast Read” and “Quad I/O Word Fast Read” command toaccess a fixed length of 8/16/32/64-byte section within a 256-byte page, in standardSPI mode.

The Set Burst withWrap command sequence: CS# goes low à Send Set Burst with Wrap command à Send 24 dummy bits à Send 8 bits “Wrap bits” à CS# goes high.

If the W6-W4 bits are set by the Set Burst with Wrap command, allthe following “Quad I/O Fast Read” and “Quad I/O Word Fast Read” command willuse the W6-W4 setting to access the 8/16/32/64-byte section within any page. Toexit the “Wrap Around” function and return to normal read operation, anotherSet Burst with Wrap command should be issued to set W4=1.

7.13. 设置带卷绕的突发模式 (77H) 设置带卷绕的突发模式命令与“四线/O快速读取”和“四线I/O字快速读取”命令配合使用，在标准SPI模式下访问256字节页面内固定长度的816/32/64字节段。 设置带卷绕的突发模式命令序列：CS# 变低  发送设置带卷绕的模式命令  发送24个虚拟位  发送8位“卷绕位”  CS# 变高。

如果W6-W4位通过Set Burst with Wrap命令设置，所有后续的“Quad I/O Fast Read”和“Qu I/O Word Fast Read”命令将使用W6-W4设置来访问任何页面内的8/16/32/64字节段。要退出Wrap Around”功能并返回到正常读取操作，应发送另一个Set Burst with Wrap命令以设置W4=1。

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7.14. Page Program (PP) (02H)

The Page Program (PP) command is forprogramming the memory. A Write Enable (WREN) command must previously have beenexecuted to set the Write Enable Latch (WEL) bit before sending the PageProgram command.

The Page Program(PP) command is entered by driving CS# Low, followed by the command code, threeaddress bytes and at least one data byte on SI. If the 8 least significantaddress bits (A7-A0) are not all zero, all transmitted data that goes beyondthe end of the current page are programmed from the start address of the samepage (from the address whose 8 least significant bits (A7-A0) are all zero).CS# must be driven low for the entire duration of the sequence. The PageProgram command sequence: CS# goes low à sending Page Program command à 3-byte address on SI à at least 1 byte data on SI à CS# goes high. The command sequence is shown in Figure18.If more than 256 bytes are sent to the device, previously latched data arediscarded and the last 256 data bytes are guaranteed to be programmed correctlywithin the same page. If less than 256 data bytes are sent to device, they arecorrectly programmed at the requested addresses without having any effects onthe other bytes of the same page. CS# must be driven high after the eighth bitof the last data byte has been latched in; otherwise the Page Program (PP)command is not executed.

As soon as CS# is driven high, theself-timed Page Program cycle (whose duration is tPP) is initiated. While the Page Programcycle is in progress, the Status Register may be read to check the value of theWrite in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during theself-timed Page Program cycle, and is 0 when it is completed. At someunspecified time before the cycle is completed, the Write Enable Latch (WEL)bit is reset.

A Page Program (PP) command applied to a page which isprotected by the Block Protect (BP4, BP3, BP2, BP1, and BP0) is not executed.

7.14. 页面编程（PP）(02H) 页面编程（PP）命令用于编程内存。发送页面编程命令之前，必须先执行写使能（WREN）命令以设置写使能寄存器（WEL）位。 通过将CS#低，然后发送命令代码、三个地址字节和至少1个数据字节到SI，可以输入页面编程（PP）命令。如果8个最低有效位地址位A7-A0）不全为零，则所有传输的数据超过当前页面末尾的部分从同一页面的起始地址开始编程（从8个最低有效位地址（A7-A0）全为零的地址开始）。CS#在整个序列期间必须保持低电平。页面编程命令序列：CS#拉低 发送页面编程命令  SI上3字节地址  SI上至少1字节数据  CS#拉高。命令序列如图18所示。如果向发送的数据超过256字节，则之前锁存的数据将被丢弃，并且保证最后256个数据字节在同一页面内正确编程。如果向设备的数据少于256个数据字节，它们将在所请求的地址正确编程，并且不会对同一页面中的其他字节产生任何影响。在最后1个数据节的第8位被锁存之后，必须将CS#拉高；否则，页面编程（PP）命令将不会执行

一旦CS#被驱动为高电平，自定时序的页面编程周期（其持续时间为tPP）将被启动。当页面编程正在进行时，可以读取状态寄存器以检查写操作进行中（WIP）位的值。在自定时序的页面编程周期中，写操作进行中WIP）位为1，当编程周期完成后为0。在编程周期完成之前某个未指定的时间点，写使能锁存器（WEL）位复位。 对受块保护（BP4、BP3、BP2、BP1和BP0）保护的页面应用页面编程（PP）命令将不被执行。